Reduction of Switching Noise in Digital CMOS Circuits by Pin Swapping of Library Cells1

The objective of this paper is to explore the applicability of a very specific design technique at a gate-level to achieve a reduction of switching noise in conventional CMOS digital circuits. The proposed technique optimizes switching noise maintaining operation speed, power consumption and transistor count. Basically, we will show how the selection of the suited pin in a gate for implementing a logic function, can bring important advantages in terms of switching noise reduction. The characterization of some CMOS 0.35 μm library cell shows different behavior regarding switching noise depending on what transitions in which input pin takes place. This has been used as the basis for a noise optimization methodology, verified through some design examples showing the noise reduction produced by the use of the proposed technique.